Semiconductor memory using field-effect transistor as selective element

ABSTRACT

A semiconductor device includes a semiconductor substrate of a first conductivity type, a first insulating film region that is embedded in a trench formed on the semiconductor substrate, a gate electrode that covers a lower surface of the first insulating film region, and a gate insulating film that is provided between the gate electrode and the semiconductor substrate. The semiconductor device further includes a first diffusion region that covers a first side surface of the first insulating film region, a second diffusion region that covers a second side surface of the first insulating film region, and a third diffusion region that covers an upper surface of the second diffusion region. A selective element includes a field-effect transistor that is constituted by the gate electrode, the first diffusion region, and the second diffusion region, and a bipolar transistor that is constituted by the substrate and the second and third diffusion regions.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, and moreparticularity relates to a semiconductor device using an IGBT (InsulatedGate Bipolar Transistor) as a selective element.

2. Description of Related Art

In recent years, a semiconductor device including a semiconductor memorydevice such as a DRAM (Dynamic Random Access Memory) and a PC-RAM (PhaseChange Random Access Memory) has an increasingly smaller area that canbe allocated to a selective element (such as a cell transistor of aDRAM) along with the progress of downscaling. As the allocated areabecomes smaller, the value of a current flowing to a selective element(such as a drain current of a field-effect transistor and a writecurrent Icell in a DRAM) becomes small. Therefore, to secure a certainlevel of the current value, constituting a selective element by acombination of a MOS (Metal Oxide Semiconductor) transistor and abipolar transistor has been examined.

U.S. Pat. No. 6,576,921 discloses an example of a cell transistor of aphase-change memory that uses such a selective element. In thisconventional example, word lines are formed on a surface of a P-typesubstrate via a gate insulating film, and first and second N-typediffusion regions are formed in a region within a substrate surfaceclose to both sides of the word lines. In the second N-type diffusionregion, a P-type diffusion region is further provided in a region withina substrate surface far from a gate electrode. With this arrangement, aMOS transistor is formed by the P-type substrate, the first and secondN-type diffusion regions, the gate insulating film, and the gateelectrode, and a bipolar transistor is formed by the P-type substrate,the second N-type diffusion region, and the P-type diffusion region. Thesecond N-type diffusion region functions as both a drain of the MOStransistor and a base of the bipolar transistor.

The P-type substrate and the first N-type diffusion region are grounded.Meanwhile, the P-type diffusion region is connected to bit lines via aphase-change memory element. When a voltage that exceeds a thresholdvalue of the MOS transistor is applied to word lines in this state, theMOS transistor is turned on, and a drain current flows. This draincurrent flows to the second N-type diffusion region, and turns on thebipolar transistor. Because the phase-change memory element is connectedto the ground, writing and reading can be performed to the phase-changememory element by controlling a voltage applied to the bit lines.

However, the selective element described in U.S. Pat. No. 6,576,921 hasa problem that the length in a lateral direction becomes large. That is,according to the configuration of the selective element described above,the first N-type diffusion region, the word lines, the second N-typediffusion region, and the P-type diffusion region are arranged in a bitline direction. Therefore, even when these regions and the word linesare formed in a minimum feature size F, respectively, the length of 4Fin the bit line direction becomes necessary. Consequently, aconfiguration capable of reducing the length of a selective element in abit line direction has been demanded.

SUMMARY

In one embodiment, there is provided a semiconductor device comprising:a semiconductor substrate of a first conductivity type; a gateinsulating film that is formed on a bottom surface of a trench formed onthe semiconductor substrate and on a part of an internal wall of thetrench; a gate electrode that is embedded in the trench so as to coverthe gate insulating film; a cap insulating film region that is embeddedin the trench so as to cover the gate electrode; first and seconddiffusion regions that are formed on a first side surface (a firstlateral) of the cap insulating film region and on a second side surface(a second lateral) opposite to the first side surface, respectively, andconstitute a field-effect transistor together with the gate electrodeand; and a third diffusion region that is formed between the second sidesurface of the cap insulating film region, an upper surface of thesemiconductor substrate, and an upper surface of the second diffusionregion and constitutes a bipolar transistor together with the substrateand the second diffusion region, wherein the field-effect transistor andthe bipolar transistor constitute a first selective element, the firstand second diffusion regions are diffusion regions of a secondconductivity type, and the third diffusion region is a diffusion regionof the first conductivity type.

In another embodiment, there is provided a semiconductor devicecomprising: a semiconductor substrate of a first conductivity type; acap insulating film region that is embedded in the semiconductorsubstrate and has a first side surface (a first lateral) perpendicularto an upper surface of the semiconductor substrate, a second sidesurface (a second lateral) opposite to the first side surface, and alower surface opposite to the upper surface of the semiconductorsubstrate; a gate electrode of which whole of a body thereof is embeddedin the semiconductor substrate and that covers a lower surface of thecap insulating film region; a gate insulating film of which whole of abody thereof is embedded in the semiconductor substrate and that isformed between the gate electrode and the semiconductor substrate; afirst diffusion region that covers the first side surface of the capinsulating film region; a second diffusion region that covers the secondside surface of the cap insulating film region; and a first selectiveelement that covers the second side surface of the cap insulating filmregion and an upper surface of the second diffusion region, and has athird diffusion region in contact with the upper surface of thesemiconductor substrate, wherein the gate electrode and the first andsecond diffusion regions constitute a field-effect transistor, thesubstrate and the second and third diffusion regions constitute abipolar transistor, the field-effect transistor and the bipolartransistor constitute a first selective element, the first and seconddiffusion regions are diffusion regions of a second conductivity type,and the third diffusion region is a diffusion region of the firstconductivity type.

In still another embodiment, there is provided a semiconductor devicecomprising: a semiconductor device of a first conductivity type; a gateinsulating film that is formed on a bottom surface of trenches formed onthe semiconductor substrate and extended in a first direction and on apart of an internal wall of these trenches; a gate electrode that isembedded in the trenches so as to cover the gate insulating film and isa word line extended in the first direction; a cap insulating filmregion that is embedded in the trenches so as to cover the gateelectrode and is extended in the first direction; a first diffusionregion of a second conductivity type and a second diffusion region of asecond conductivity type that are formed respectively on a part of afirst second-directional side surface of the cap insulating film regionand on a part of a second second-directional side surface opposite to apart of the first second-directional side surface and constitute afield-effect transistor together with the corresponding gate electrode,the second direction being orthogonal to the first direction; a thirddiffusion region of the first conductivity type that is formed between apart of the second second-directional side surface of the cap insulatingfilm region, an upper surface of the semiconductor substrate, and anupper surface of the second diffusion region, and constitutes a bipolartransistor together with the substrate and the corresponding seconddiffusion region; a plurality of bit lines extended in the seconddirection; an active region that is partitioned in at least a part of aregion below the bit lines by a first element isolation region (a firstisolation region of elements) formed between the bit lines; and aplurality of memory elements that correspond respectively to one ofintersections of the bit lines and the word lines, and are connected tothe corresponding third diffusion region included in the active region,wherein a plurality of the field-effect transistors and a plurality ofthe bipolar transistors that respectively correspond to the field-effecttransistors, each included in the active region, constitute a pluralityof selective elements, and the memory elements and the selectiveelements that respectively correspond to the memory elements constitutea plurality of memory cells.

According to the present invention, a field-effect transistor is formedby a semiconductor substrate, first and second diffusion regions, gateinsulating films, and gate electrodes. A bipolar transistor is formed bya semiconductor substrate and the second and third diffusion regions.The second diffusion region functions as both a controlled electrode ofone of field-effect transistors and as a base of a bipolar transistor.Because the second and third diffusion regions are arranged in a normaldirection of the semiconductor substrate, 3F is sufficient for thelength of the selective element in an arranging direction (the bit linedirection) of the first diffusion region, the gate electrode, and thesecond diffusion region (the third diffusion region). Therefore, thelength of the selective element in the bit line direction can bereduced.

BRIEF DESCRIPTION OF THE DRAWINGS

The above features and advantages of the present invention will be moreapparent from the following description of certain preferred embodimentstaken in conjunction with the accompanying drawings, in which:

FIGS. 1 and 2 are plan views of a semiconductor device according to afirst embodiment of the present invention;

FIGS. 3A to 3C are cross-sectional views of the semiconductor devicecorresponding to a cross section along a line A-A′, a cross sectionalong a line B-B′, and a cross section along a line C-C′ shown in FIGS.1 and 2, respectively;

FIG. 4 is an explanatory diagram of a relationship between aconfiguration of the semiconductor device shown in FIG. 3 and circuitelements of the semiconductor device shown in FIG. 5;

FIG. 5 is an equivalent circuit diagram of the semiconductor deviceaccording to a first embodiment of the present invention;

FIG. 6A shows temporal changes of an electric potential in lines and atnodes in case of phase-changing the memory element of the memory cell tobe selected to an amorphous phase (Reset);

FIG. 6B shows temporal changes of an electric potential in lines and atnodes in case of phase-changing the memory element of the memory cell tobe selected to a crystalline phase (Set);

FIG. 7A shows temporal changes of an electric potential in lines and atnodes in case of reading memory information from the memory element thattakes an amorphous phase;

FIG. 7B shows temporal changes of an electric potential in lines and atnodes in case of reading memory information from the memory element thattakes a crystalline phase;

FIG. 8 is a plan view of the semiconductor device according to a secondembodiment of the present invention;

FIGS. 9A to 9C are cross-sectional views of the semiconductor devicecorresponding to a cross section along a line A-A′, a cross sectionalong a line B-B′, and a cross section along a line C-C′ shown in FIG.8, respectively;

FIGS. 10 and 11 are plan views of the semiconductor device according toa third embodiment of the present invention;

FIGS. 12A to 12C are cross-sectional views of the semiconductor devicecorresponding to a cross section along a line A-A′, a cross sectionalong a line B-B′, and a cross section along a line C-C′ shown in FIGS.10 and 11, respectively;

FIG. 13 is a plan view of the semiconductor device according to a fourthembodiment of the present invention; and

FIGS. 14A to 14C are cross-sectional views of the semiconductor devicecorresponding to a cross section along a line A-A′, a cross sectionalong a line B-B′, and a cross section along a line C-C′ shown in FIG.13, respectively.

DETAILED DESCRIPTION OF THE EMBODIMENTS

A representative example of a technical concept for solving the problemof the present invention is described below. It is needless to mentionthat the contents that the present application is to claim for patentare not limited to the following technical concept, but are as describedin the appended claims. That is, as shown in FIG. 4, a semiconductordevice according to the present invention includes: embedded word linesWL (gate electrodes) each of which having a so-called gap insulatingfilm 11 formed on a semiconductor substrate (of a first conductivitytype); first and second diffusion regions 15 and 16 (both are of asecond conductivity type) that are formed at both sides of a capinsulating film region and constitute a field-effect transistor togetherwith a gate electrode; and third diffusion regions 17 (of the firstconductivity type) each of which is formed between one side surface ofthe cap insulating film region, an upper surface of the semiconductorsubstrate, and an upper surface of the second diffusion region, andconstitutes a bipolar transistor together with the substrate and thesecond diffusion region. The field-effect transistor and the bipolartransistor constitute a first selective element. Memory elements 20 arerespectively connected to each of the third diffusion regions. Thesecond diffusion region works as one of controlled electrodes of afield-effect transistor and as a base electrode of a bipolar transistor.

Based on this configuration, the field-effect transistor is formed bythe semiconductor substrate, the first and second diffusion regions, agate insulating film, and a gate electrode, and a bipolar transistor isformed by the semiconductor substrate and the second and third diffusionregions. The second diffusion region works as one of controlledelectrodes of the field-effect transistor and as a base electrode of thebipolar transistor. Because the second and third diffusion regions arearranged in a normal direction of the semiconductor substrate, 3F issufficient for the length of a selective element in an arrangingdirection (bit line direction) of the first diffusion region, the gateelectrode, and the second diffusion region (third diffusion region).Therefore, the length of the selective element in the bit line directioncan be reduced.

As shown in FIGS. 1 and 4, another example of a semiconductor deviceaccording to the technical concept for solving a problem of the presentinvention includes: a gate insulating film 14 (represented by a thicksolid line) that is formed on a bottom surface of trenches which areformed on a semiconductor substrate (of P-type) and are extended in an Xdirection and on a part of an internal wall of these trenches; the gateelectrodes 23 as the word lines WL that are embedded in the trenches soas to cover the gate insulating film and are extended in the Xdirection; the cap insulating film regions 11 of which trenches areembedded so as to cover the gate electrodes and that are extended in theX direction; the first diffusion regions 15 (of N-type) and the seconddiffusion regions 16 (of N-type) that are formed respectively on a partof a first Y directional side surface (the Y direction is orthogonal tothe X direction) of the cap insulating film regions and on a part of asecond side surface opposite to the part of the side surface andconstitute a field-effect transistor together with a corresponding gateelectrode; the third diffusion regions 17 (of P-type) each of which isformed between a part of the second Y directional side surface of thecap insulating film region, an upper surface of the semiconductorsubstrate, and an upper surface of the second diffusion region, andconstitutes a bipolar transistor together with the substrate and acorresponding second diffusion region; plural bit lines BL extendedrespectively in the Y direction; an active region K that is partitionedin at least a part of a lower region of the bit lines by an elementisolation region 12 (an isolation region 12 of elements) formed betweenthe bit lines; and plural memory elements 20 that correspondrespectively to one of intersections of bit lines and word lines and areconnected to the corresponding third diffusion region included in theactive region. Plural selective elements are constituted by pluralfield-effect transistors and plural bipolar transistors respectivelycorresponding to the plural field-effect transistors includedrespectively in the active region K, and plural memory cells areconstituted by plural memory elements and plural selective elementsrespectively corresponding to the plural memory elements.

The length of the selective element in the bit line direction can bealso reduced by the above configuration. Because a region between wordlines is embedded with a semiconductor of a first conductivity typeinstead of a dielectric, capacitance coupling between the word lines isreduced, and coupling noise generated by the capacitance coupling isreduced.

Preferred embodiments of the present invention will be explained belowin detail with reference to the accompanying drawings.

FIG. 1 is a plan view of a semiconductor device 1 according to a firstembodiment of the present invention. To facilitate understanding of aconfiguration of the semiconductor device 1, FIG. 1 shows variousconstituent elements in a transparent manner and omits various otherconstituent elements. FIG. 2 is also a plan view of the semiconductordevice 1 according to the first embodiment. FIG. 2 facilitates aconfiguration of an element isolation region described later, andsubstantially omits constituent elements other than the elementisolation region. FIGS. 3A to 3C are cross-sectional views of thesemiconductor device 1 corresponding to a cross section along a lineA-A′, a cross section along a line B-B′, and a cross section along aline C-C′ shown in FIGS. 1 and 2, respectively.

The semiconductor device 1 is a PC-RAM having the memory elements 20each including phase-change memory elements, and is provided on asurface of a P-type (first conductivity type) semiconductor (silicon)substrate 10 as shown in FIG. 1 and others. In the present invention,the P-type semiconductor substrate 10 includes a P-type diffusion region(Pwell) provided on a silicon substrate surface. FIGS. 1 and 2 showportions near a corner of a memory mat of a PC-RAM.

A circuit configuration of the semiconductor device 1 is explainedfirst.

FIG. 5 is an equivalent circuit diagram of the semiconductor device 1.FIG. 5 shows only four memory cells. As shown in FIG. 5, thesemiconductor device 1 includes plural word lines WL arranged in the Xdirection, the plural bit lines BL arranged in the Y direction, andplural memory cells MC arranged at intersections of the word lines WLand the bit lines BL.

As shown in FIG. 5, each of the memory cells MC has the memory element20 and a selective element 21 (first selective element). The memoryelement 20 is configured to include a phase change material. The phasechange material is not particularly limited when the material has two ormore phase states and also when an electric resistance is differentdepending on a phase state. A so-called calcogenide material ispreferably selected. The calcogenide material can selectively take aphase state of a relatively high-resistance amorphous phase or arelatively low-resistance crystalline phase, and is an alloy containingat least one of germanium (Ge), antimony (Sb), tellurium (Te), indium(In), and selenium (Se). For example, there are binary alloys such asGaSb, InSb, InSe, Sb₂Te₃, and GeTe, ternary alloys such as Ge₂Sb₂Te₅,InSbTe, GaSeTe, SnSb₂Te₄, and InSbGe, and quaternary alloys such asAgInSbTe, (GeSn)SbTe, GeSb(SeTe), and Te₈₁Ge₁₅Sb₂S₂.

One end of each of the memory elements 20 is connected to the bit lineBL, and the other end is connected to the selective element 21.

The selective element 21 has a PNP-type bipolar transistor 22 and anN-channel MOS transistor 23, thereby constituting a so-called IGBT(Insulated Gate Bipolar Transistor). Detailed configurations andconstituent materials of the selective element 21 are described later.

An emitter E of each bipolar transistor 22 is connected to the memoryelement 20, and a collector C of the transistor is connected to a groundwiring. A base B of the bipolar transistor 22 is connected to a drain D(one controlled electrode) of the MOS transistor 23. A gate G (controlelectrode) of the MOS transistor 23 is connected to the word line WL,and a source S (the other controlled electrode) of the transistor isconnected to a ground wiring (the semiconductor substrate 10). In thefollowing explanations, a connection point between the bipolartransistor 22 and the memory element 20 is called an emitter node EN,and a connection point between the bipolar transistor 22 and the MOStransistor 23 is called a base node BN.

When the memory cell MC is selected, the word line WL connected to thegate electrode G of the memory cell MC to be selected is activated (setat a high electric potential). A drain current flows to the MOStransistor 23, the bipolar transistor 22 is turned on, and the emitternode EN is connected to the ground wiring. Accordingly, the memoryelement 20 is connected between the bit line BL and the ground wiring.Therefore, it becomes possible to control a phase state of the memoryelement 20 (write) by controlling an amount of a current to be passed tothe bit line BL, and to detect a phase state of the memory element 20(read) by detecting an amount of a current flowing through the bit lineBL by a sense amplifier (not shown).

Because the IGBT is used for the selective element 21 in this way, acurrent value of the current Icell that flows to the memory element 20can be increased as compared with a current value when only a MOStransistor is used for the selective element 21. That is, the currentIcell becomes a current which is obtained by amplifying a drain currentof the MOS transistor 23 by the bipolar transistor 22. Therefore, thecurrent value of the current Icell becomes larger than the current valueof the drain current of the MOS transistor 23.

A change of a voltage in each line and at each node when writing orreading to or from the memory cell MC is explained next.

FIGS. 6A and 6B and 7A and 7B show temporal changes of an electricpotential in lines and at nodes. FIG. 6A shows a case of phase-changingthe memory element 20 of the memory cell MC to be selected to anamorphous phase (Reset), and FIG. 6B shows a case of phase-changing thememory element 20 to a crystalline phase (Set). FIG. 7A shows a case ofreading memory information from the memory element 20 that takes anamorphous phase, and FIG. 7B shows a case of reading memory informationfrom the memory element 20 that takes a crystalline phase. In thesedrawings and the following explanations, “selective WL” and “selectiveBL” represent the word line WL and the bit line BL that are connected tothe memory cell MC to be selected, respectively. “Non-selective WL” and“non-selective BL” respectively represent the word line WL and the bitline BL, which are not “selective WL” and not “selective BL”. “EN” and“BN” shown in these drawings denote the emitter node EN and the basenode BN of the memory cell MC to be selected, respectively.

The following Table 1 is a list of electric potentials of lines andnodes. In Table 1 and in the following explanations, “selective cell”represents the memory cell MC to be selected, “non-selective cell B”represents the memory cell MC that shares the bit line BL with“selective cell”, and “non-selective cell W” represents the memory cellMC that shares a word line with “selective cell”, respectively.

TABLE 1 At Write time Read time standby Non- Non- Non- Non- Wholeselective Selective selective selective Selective selective cells cell Bcell cell W cell B cell cell W WL −0.3 V −0.3 V 2.4 V −0.3 V 2.4 V (VKK)(VKK) (VWL) (VKK) (VWL) BL 0.0 V About 5.0 V 0.0 V About 1.5 V 0.0 V(VSS) (VPP) (VSS) (VRead) (VSS) Emitter 0.0 V About 1.1 V + α 0.0 VAbout About 0.0 V node (VSS) 5.0 V (VSS) 1.5 V 1.1 V (VSS) (VPP) BaseFloating About +α 0.0 V About About 0.0 V node 4 V (VSS) 0.5 V 0 V (VSS)(Floating) (Floating) Collect 0.0 V 0.0 V +β 0.0 V 0.0 V About 0.0 V or(VSS) (VSS) (VSS) (VSS) 0 V (VSS) Source 0.0 V (VSS)

As shown in FIGS. 6A and 6B and 7A and 7B, and in Table 1, in a standbystate, electric potentials of the word line WL and the bit line BLbecome VKK (=−0.3 V) and VSS (=0.0 V), respectively. The bipolartransistor 22 and the MOS transistor 23 of each of the memory cells MCare off, respectively. The base node BN is floating, and an electricpotential of the emitter node EN becomes the same VSS as that of the bitline BL. Electric potentials of the collector and the source are VSS ofthe ground wiring.

At the write time, an electric potential of VWL (=2.4 V) is given to theselective WL. Accordingly, in the selective cell, the bipolar transistor22 and the MOS transistor 23 become on, and the emitter node EN isconnected to the ground wiring.

When phase-changing the memory element 20 of the selective cell to anamorphous phase, an electric potential of the selective BL is increasedto VPP (about 5.0 V), and thereafter is returned to VSS at a high speed,as shown in FIG. 6A. Accordingly, the memory element 20 instantlychanges from a state of passing the current Icell to a state of notpassing the current Icell. Because the memory element 20 is rapidlycooled by the instant change of the current Icell, its phase statechanges to an amorphous phase.

Meanwhile, in phase-changing the memory element 20 of the selective cellto a crystalline phase, an electric potential of the selective BL isincreased to VPP, and thereafter is gradually returned to VSS by takinga long time, as shown in FIG. 6B. Because the memory element 20 iscooled by taking a long time after being heated, a phase state of thememory element 20 changes to a crystalline phase.

An electric potential of the emitter node EN of the selective cell atthe write time becomes 1.1 V+α (α=about 0.2 V) as shown in Table 1. α isan electric potential that is generated in the base node BN when thecurrent Icell flows. An electric potential of the collector of theselective cell becomes +β as shown in Table 1. β is also an electricpotential that is generated when the current Icell flows, and its valueis permitted up to about 1.0 V.

Regarding the non-selective cell B at the write time, electricpotentials are the same as those at the standby time, except that anelectric potential of the emitter node EN becomes the same VPP as theelectric potential of the bit line and that an electric potential of thebase node BN becomes about 4 V, as shown in Table 1. On the other hand,regarding the non-selective cell W at the write time, electricpotentials of the emitter node EN, the base node BN, and the collectorall become VSS because the current Icell does not flow while theselective element 21 becomes on.

At the read time, an electric potential of VWL is also given to theselective WL. Accordingly, in the selective cell, both the bipolartransistor 22 and the MOS transistor 23 become on, and the emitter nodeEN is connected to the ground wiring.

Thereafter, an electric potential of VRead (about 1.5 V) is given to theselective BL, as shown in FIGS. 7A and 7B. Accordingly, the currentIcell flows to the selective cell. Specifically, an electric potentialof VRead is determined such that a current value of the current Icellbecomes small to an extent that a phase state of the memory element 20does not change.

An electric potential of the selective BL becomes low when the currentIcell flows. When the memory element 20 is in an amorphous phase (a highresistance state), a current value of the current Icell becomesrelatively small, and a reduction of the electric potential of theselective BL becomes small. Therefore, as shown in FIG. 7A, a reductionof the current of the selective BL is little observed. On the otherhand, when the memory element 20 is in a crystalline phase (a lowresistance state), a current value of the current Icell becomesrelatively large. Therefore, a reduction of the current of the selectiveBL is observed as shown in FIG. 7B.

An electric potential of the emitter node EN of the selective cell atthe read time becomes about 1.1 V as shown in Table 1. Although electricpotentials of the base node BN and the collector of the selective cellbecome floating because the current Icell flows, these electricpotentials become about substantially 0 V because the current Icell atthe read time is small as described above.

Regarding the non-selective cell B at the read time, electric potentialsare identical to those at the standby time, except that an electricpotential of the emitter node EN becomes about 1.5 V that is the same asthe electric potential of the bit line and that an electric potential ofthe base node BN becomes about 0.5 V, as shown in Table 1. On the otherhand, regarding the non-selective cell W at the read time, electricpotentials of the emitter node EN, the base node BN, and the collectorbecome VSS, respectively because the current Icell does not flow whilethe selective element 21 becomes on.

The configuration of the semiconductor device 1 is explained next.

As shown in FIG. 1, the semiconductor device 1 has plural word lines WLthat are arranged in the X direction and plural bit lines BL that arearranged in the Y direction. Each of the word lines WL is a linearconductor that is extended in the X direction and is constituted by amaterial such as doped polysilicon, for example. On the other hand, eachof the bit lines BL is a linear conductor that is extended in the Ydirection and is constituted by a metal material such as copper (Cu),for example.

Although not shown in the drawing, row decoders are provided at bothends of a memory mat in the X direction, and the word lines WL arealternately connected to the row decoders at both ends. Similarly,column decoders are provided at both ends of the memory mat in the Ydirection, and the bit lines BL are alternately connected to the columndecoders at both ends.

Every third word line WL is a dummy word line DWL. The word lines WLincluding the dummy word lines DWL are arranged at equal distances. Thatis, two word lines WL and one dummy word line DWL form a unitconfiguration. This unit configuration is repeatedly arranged in the Ydirection. The dummy word lines DWL are provided because it is desirableto set wiring densities of the word lines WL constant to secure asatisfactory processing condition and to employ an arrangement (to bedescribed later) in which an area occupied per one memory cell MCbecomes 6F² (F is a minimum feature size).

The word lines WL (including the dummy word lines DWL) are embedded intothe semiconductor substrate 10 as shown in FIGS. 3A and 3B. Theinsulating film regions 11 (cap insulating film regions) that areextended in the X direction are provided along an upper surface of theword lines WL (its definition is a surface side of the substrate).Silicon nitride or silicon oxide is preferably used for the constituentmaterial of the insulating film regions 11. The insulating film regions11 are also embedded into the semiconductor substrate 10 as shown inFIGS. 3A and 3B. All bodies of the word lines WL are embedded beneaththe surface of the substrate. All side surfaces (an upper surface, bothside surfaces, and a lower surface (a bottom surface)) of the word linesWL are included in the substrate. A part of a body of each insulatingfilm region 11 is embedded beneath the surface of the substrate. Bothside surfaces and a lower surface of each insulating film region 11 as apart of the body are included in the substrate. An upper surface of theinsulating film region 11 is at the same position as a position of thesurface of the substrate. In the present application, the insulatingfilm region 11 of which both side surfaces and a lower surface excludingan upper surface are included in the substrate is explained as “theinsulating film region 11 embedded in the substrate”. This is similarlyapplied to the element isolation regions 12 described later. The uppersurface means a side that is close to a surface side of the substrate.The lower surface means a side that is far from the surface of thesubstrate. The side surface means a surface perpendicular to the surfaceof the substrate. These are similarly applied to the followingexplanations.

The element isolation region 12 (first element isolation region) that islong in the Y direction is provided between the bit lines BL as shown inFIG. 2. The element isolation regions 12 are provided to partition theactive region K as a region that forms the memory cell MC. Siliconnitride or silicon oxide is preferably used for the constituent materialof the element isolation region 12. From a first viewpoint, each activeregion K is defined (partitioned) between the element isolation regions12. The element isolation region 12 is also embedded into thesemiconductor substrate 10 as shown in FIGS. 3B and 3C. Both sidesurfaces and a lower surface of the element isolation region 12 areincluded in the substrate, and an upper surface is the same as thesurface of the substrate.

From a second viewpoint, the active regions K are partitioned by theinsulating film regions 11 that are formed along an upper surface of thedummy word lines DWL. Two word lines WL are arranged in one activeregion K. Two selective elements 21 (first and second selectiveelements) that uses each of the two word lines WL as its gate electrode,and two memory cells (first and second memory cells) that use theseselective elements 21, respectively are formed in one active region K. Aconfiguration within the active region K is explained in detail withreference to FIGS. 3A, 3B, and 3C.

The selective element 21 includes the word line WL (gate electrode) thatcovers a lower surface 11c of the insulating film region 11, and thegate insulating film 14 (see FIG. 3A) that is provided between the wordline WL and the semiconductor substrate 10. The gate insulating film 14is shown by a thick solid line. The gate insulating film 14 ispreferably constituted by providing a trench in the semiconductorsubstrate 10 to form the word line WL and thereafter by oxidizing aninternal wall of the trench. Except in FIG. 3A, reference numeral “14”is not attached to the gate insulating film.

The selective element 21 further includes the first to third diffusionregions 15 to 17. The first diffusion region 15 is an N⁻-type (N minustype) impurity diffusion region that covers a side surface 11a of theinsulating film region 11 in the bit-line direction (a side surfaceopposite to the other selective element 21 in the active region K), andis provided in contact with the side surface 11a. The second diffusionregion 16 is an N⁻-type impurity diffusion region that covers a sidesurface 11b of the insulating film region 11 in the bit-line direction(a side surface at an opposite side of the side surface 11a), and isprovided in contact with the side surface 11b. The third diffusionregion 17 is a P⁺-type (P plus type) impurity diffusion region thatcovers an upper surface of the second diffusion region 16, and isprovided in contact with the upper surface of the second diffusionregion 16.

The first and second diffusion regions 15 and 16 are formed byimplanting an N-type (second conductivity type) impurity into thesurface of the semiconductor substrate 10. The third diffusion region 17is formed by implanting an impurity of the same conductivity-type(P-type) as that of the semiconductor substrate 10 on the surface of thesecond diffusion region 16.

It is preferable that the N-type impurity is simultaneously implantedinto the first and second diffusion regions 15 and 16. With thisarrangement, the total of the length of the second diffusion region in aZ direction and the length of the third diffusion region 17 in the Zdirection becomes substantially the same as the length of the firstdiffusion region 15 in the Z direction. Conversely, it becomes possibleto implant the N-type impurity simultaneously into the first and seconddiffusion regions 15 and 16 by uniforming the total of the length of thesecond diffusion region in a Z direction and the length of the thirddiffusion region 17 in the Z direction with the length of the firstdiffusion region 15 in the Z direction.

Based on the above configuration, the MOS transistor 23 is formed by thesemiconductor substrate 10, the first and second diffusion regions 15and 16, the gate insulating film 14, and the word line WL. The bipolartransistor 22 is formed by the semiconductor substrate 10 and the secondand third diffusion regions 16 and 17.

FIG. 4 is an explanatory diagram of a relationship between aconfiguration of the semiconductor device 1 shown in FIG. 3 and circuitelements of the semiconductor device 1 shown in FIG. 5. FIG. 4 showscircuit elements such as the bipolar transistors 22 that aresuperimposed on the cross-sectional view shown in FIG. 3A. As shown inFIG. 4, the first diffusion region 15 constitutes a source of the MOStransistor 23, and the second diffusion region 16 constitutes a drain ofthe MOS transistor 23 and a base of the bipolar transistor 22. The thirddiffusion region 17 constitutes an emitter of the bipolar transistor 22,and the semiconductor substrate 10 constitutes a collector of thebipolar transistor 22.

The collector of the bipolar transistor 22 and the source of the MOStransistor 23 are grounded as are also shown in FIG. 4. This groundingis achieved by connecting the semiconductor substrate 10 and the firstdiffusion region 15 to the ground wiring VSS. Specifically, as shown inFIG. 1, some of the bit lines BL are used for the ground wiring VSS. Thesemiconductor substrate 10 and the first diffusion regions 15 areconnected to the ground wirings VSS by contact conductors 30 and 31,respectively.

Two selective elements 21 are provided in one active region K asdescribed above. As a detailed configuration, the two selective elements21 share the first diffusion region as shown in FIG. 4. One selectiveelement 21 has a symmetrical structure with the other selective element21 across the first diffusion region 15. By employing thisconfiguration, in the semiconductor device 1, a distance from the thirddiffusion region 17 of one selective element 21 to the third diffusionregion 17 of the other selective element 21 becomes 5F. Therefore, inthe semiconductor device 1, an occupied area per one active region Kbecomes 6F².

Lower surfaces of the first and second diffusion regions 15 and 16 areprovided at a higher position than that of the upper surface of the wordline WL as shown in FIG. 4. That is, the first and second diffusionregions 15 and 16 and the word line WL are not adjacent to each otheracross the gate insulating film 14. This arrangement is provided toprevent an occurrence of a parasitic transistor. That is, if the wordline WL (gate electrode) and the second diffusion region 16 are adjacentto each other across the gate insulating film 14, for example, a MOStransistor (parasitic transistor) is formed which has the word line WLas a control electrode and has the third diffusion region 17 and thesemiconductor substrate 10 as non-control electrodes. Formation of thisparasitic transistor is not desirable. Therefore, as described above,the lower surfaces of the first and second diffusion regions 15 and 16are set at a higher position than that of the upper surface of the wordline WL, thereby preventing formation of a parasitic transistor, asdescribed above.

Each of the memory elements 20 is formed on an upper surface of thethird diffusion region 17 of the corresponding selective element 21.Specifically, a contact conductor 32 is formed on the upper surface ofthe third diffusion region 17, and a lower electrode UE is formed on anupper surface of the contact conductor 32, as shown in FIGS. 3A and 3C.A phase-change memory element GST made of a phase change materialdescribed above is formed on an upper surface of the lower electrode UE.An upper electrode TE that is common to the memory elements 20 arrangedin the bit line direction (the Y direction) is formed on an uppersurface of the phase-change memory element GST. The memory element 20 isconstituted by the lower electrode UE, the phase-change memory elementGST, and the upper electrode TE. The upper electrode TE is electricallyconnected to the bit line BL by a contact conductor 33.

For a material of the lower electrode UE, a material having a relativelyhigh electric resistance such as metal silicide, metal nitride, and anitride of metal silicide, for example is preferably used. Although notparticularly limited, a high melting-point metal such as W, TiN, TaN,WN, and TiAlN, a nitride of these high melting-point metals, a nitrideof a high melting-point silicide such as TiSiN, WSiN, and a materialsuch as TiCN can be preferably used. A metal material having arelatively low electric resistance is preferably used for a material ofthe upper electrode TE. For example, aluminum (Al), titanium (Ti),tungsten (W), an alloy of these metals, and a nitride or silicide ofthese metals can be preferably used.

As explained above, in the semiconductor device 1 according to the firstembodiment, the second and third diffusion regions 16 and 17 arearranged in the normal direction (the Z direction) of the semiconductorsubstrate 10. Therefore, 3F (F is a minimum feature size) is sufficientfor the length of the selective element 21 in the bit line direction(the X direction). Consequently, the length of the selective element 21in the bit line direction (the X direction) can be shortened as comparedwith the length according to the conventional technique.

As described above, in the semiconductor device 1 according to the firstembodiment, formation of a parasitic transistor attributable to the wordline WL and the first and second diffusion regions 15 and 16 beingadjacent to each other across the gate insulating film 14 can beprevented.

Further, because a region between the word lines WL is embedded with theP-type semiconductor substrate 10 not with a dielectric, capacitancecoupling between the word lines WL can be reduced and coupling noisegenerated by the capacitance coupling can be reduced.

FIG. 8 is a plan view of the semiconductor device 1 according to asecond embodiment of the present invention. FIG. 8 corresponds to FIG. 2shown in the first embodiment. FIGS. 9A to 9C are cross-sectional viewsof the semiconductor device 1 corresponding to a cross section along aline A-A′, a cross section along a line B-B′, and a cross section alonga line C-C′ shown in FIG. 8, respectively.

As shown in FIGS. 8 and 9, the semiconductor device 1 according to thesecond embodiment is different from the semiconductor device 1 accordingto the first embodiment in that the semiconductor device 1 according tothe second embodiment additionally includes element isolation regions 13(second and third element isolation regions) and excludes the dummy wordlines DWL and the insulating film regions 11 on the dummy word linesDWL.

Each of the element isolation regions 13 replaces the dummy word line WLand a portion on the dummy word line DWL in the first embodiment, asshown in FIGS. 8, 9A, and 9B. That is, the element isolation regions 13are arranged to sandwich two word lines WL.

By providing the element isolation regions 13, the active region K thatis identical to that in the first embodiment can be partitioned withoutusing the dummy word lines DWL. Because the dummy word lines DWL are notused, capacitance coupling between the dummy word line DWL and the wordline WL can be avoided.

FIGS. 10 and 11 are plan views of the semiconductor device 1 accordingto a third embodiment of the present invention. FIGS. 10 and 11correspond to FIGS. 1 and 2 shown in the first embodiment. FIGS. 12A to12C are cross-sectional views of the semiconductor device 1corresponding to a cross section along a line A-A′, a cross sectionalong a line B-B′, and a cross section along a line C-C′ shown in FIGS.10 and 11, respectively.

As shown in FIGS. 10 to 12, the semiconductor device 1 according to thethird embodiment is different from the semiconductor device 1 accordingto the first embodiment in that the element isolation regions 12, thefirst diffusion regions 15, and the contact conductors 31 are replacedby element isolation regions 12a, first diffusion regions 15a, andcontact conductors 31a, respectively, and that slit-shaped contactconductors 34 (hereinafter, simply “contact conductors”) are added.Other features of the semiconductor device 1 according to the thirdembodiment are identical to those of the semiconductor device 1according to the first embodiment.

The element isolation regions 12a are extended in the Y direction froman end to an end of a memory mat without a break through a lower end ofthe contact conductors 34. By constituting the element isolation regions12a in this way, the first diffusion regions 15a are divided by theelement isolation regions 12a.

To connect the divided first diffusion regions 15a to the ground wiringsVSS, in the third embodiment, the contact conductors 34 for mutuallyconnecting the first diffusion regions 15a arranged in the X directionare formed on the surface of the semiconductor substrate 10, as shown inFIGS. 10, 12A and 12B. Each of the contact conductors 31a connects thecontact conductor 34 and the ground wiring VSS.

According to the semiconductor device 1 of the third embodiment,preparation of a mask pattern to be used when forming the elementisolation regions 12a becomes easy because the element isolation regions12a are continuously extended from an end to an end of the memory mat.

FIG. 13 is a plan view of the semiconductor device 1 according to afourth embodiment of the present invention. FIG. 13 corresponds to FIG.1 described in the first embodiment. FIGS. 14A to 14C arecross-sectional views of the semiconductor device 1 corresponding to across section along a line A-A′, a cross section along a line B-B′, anda cross section along a line C-C′ shown in FIG. 13, respectively.

As shown in FIGS. 13 and 14, the semiconductor device 1 according to thefourth embodiment is different from the semiconductor device 1 accordingto the first embodiment in that the first diffusion regions 15 arereplaced by the first diffusion regions 15b. Other features of thesemiconductor device 1 according to the fourth embodiment are identicalto those of the semiconductor device 1 according to the firstembodiment.

The first diffusion regions 15b are provided by performing salicideprocessing on the first diffusion regions 15. The salicide processing isperformed by depositing a metal such as Ti and Co by several tens ofnanometers by a sputtering method after forming the first diffusionregions 15 by implanting an N-type impurity into the surface of thesemiconductor substrate 10, and by forming silicide 18 on the surface ofthe metal by reacting the metal with silicon by annealing.

By using the first diffusion regions 15b having the salicide processingperformed thereon, a contact resistance between the first diffusionregion 15b and the contact conductor 31 can be lowered.

It is apparent that the present invention is not limited to the aboveembodiments, but may be modified and changed without departing from thescope and spirit of the invention.

The technical concept of the present invention can be also applied to,for example, an RE-RAM (Resistance Random Access Memory) in addition toa PC-RAM explained in the above embodiments. Further, the presentinvention can be also applied to an IGBT and an FET that are related toa memory element that passes a relatively large current to a memorycell. In addition, the type of the memory element is not limited to anonvolatile memory element.

The technical concept of the present invention can be applied to varioustypes of semiconductor devices. For example, the present invention canbe applied to a general semiconductor device such as a CPU (CentralProcessing Unit), an MCU (Micro Control Unit), a DSP (Digital SignalProcessor), an ASIC (Application Specific Integrated Circuit), an ASSP(Application Specific Standard Circuit), and a Memory device. An SOC(System on Chip), an MCP (Multi Chip Package), and a POP (Package onPackage) and so on are pointed to as examples of types of semiconductordevice to which the present invention is applied. The present inventioncan be applied to the semiconductor device that has these arbitraryproduct form and package form.

Furthermore, although an example in which a selective element has a MOStransistor has been explained in the above embodiments, the presentinvention is not limited thereto as long as the transistor is afield-effect transistor (FET). That is, other than a MOS (Metal OxideSemiconductor), the present invention can be also applied to varioustypes of FETs such as a MIS (Metal-Insulator Semiconductor) and a TFT(Thin Film Transistor).

In the above embodiments, although P-type and N-type have been explainedas the first conductivity type and the second conductivity type,respectively, this relationship can be opposite. That is, N-type andP-type can be the first conductivity type and the second conductivitytype, respectively. In this case, an N-type semiconductor substrate isused for the semiconductor substrate 10, and the first to thirddiffusion regions 15 to 17 become P-type, P-type, and N-type,respectively. Therefore, the bipolar transistors 22 become NPN type, andthe MOS transistors 23 become P-channel type.

Many combinations and selections of various constituent elementsdisclosed in this specification can be made within the scope of theappended claims of the present invention. That is, it is needles tomention that the present invention embraces various changes andmodifications which can be made by those skilled in the art based on theentire disclosure of this specification including the claims and thetechnical concept of the invention.

In addition, while not specifically claimed in the claim section, theapplicant reserves the right to include in the claim section of theapplication at any appropriate time the following devices:

A1. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type including atrench that extends to a first direction, the trench having a bottomsurface and an inner wall;

a gate insulating film that is formed on the bottom surface and a partof the inner wall of the trench;

a gate electrode that is embedded in a lower portion of the trenches soas to cover the gate insulating film, the gate electrode being served asa word line extending to the first direction;

a cap insulating film that is embedded in an upper portion of thetrenches so as to cover the gate electrode and extending to the firstdirection;

a plurality of first diffusion regions of a second conductivity typeopposite to the first conductivity type that are formed in thesemiconductor substrate and each located on a part of a first sidesurface of the first cap insulating film;

a plurality of second diffusion regions of the second conductivity typethat are formed in the semiconductor substrate and each located on apart of a second side surface of the first cap insulating film;

a plurality of third diffusion regions of the first conductivity typethat is formed in the semiconductor substrate each located on anotherpart of the second side surface of the first cap insulating film andeach located between an upper surface of the semiconductor substrate andan associated of upper surfaces of the second diffusion regions;

a plurality of bit lines extending to a second direction opposite to thefirst direction;

a plurality of active regions formed in the semiconductor substrate eachformed below an associated one of bit lines, the active regions beingpartitioned by a first element isolation region formed between a regionbelow the bit lines; and

a plurality of memory elements that correspond respectively to one ofintersections of the bit lines and the word lines, each of the memoryelements being connected to an associated one of the third diffusionregions and formed in the active regions, wherein

corresponding ones of the first and second diffusion regions and thefirst gate electrode constitute a field-effect transistor,

corresponding ones the second and third diffusion regions and thesemiconductor substrate constitute a bipolar transistor,

the first and second side surfaces are opposite to each other in thesecond direction,

the field-effect transistors and the bipolar transistors thatrespectively correspond to the field-effect transistors constitute aplurality of selective elements, and

the memory elements and the selective elements that respectivelycorrespond to the memory elements constitute a plurality of memorycells.

A2. The semiconductor device in A1, wherein the memory cells includefirst and second memory cells that share the first diffusion region,have mutually symmetrical structures using the first diffusion region asan axis, and are adjacent to each other in the second direction.

A3. The semiconductor device in A2, wherein

a plurality of the word lines are provided,

the word lines are arranged at an equal interval in the seconddirection,

the word lines have two of the word lines related to the first andsecond memory cells as a group, and

the word lines further include dummy word lines that are arrangedbetween two of the groups and do not make field-effect transistorsconstituted by the dummy word lines conductive.

A4. The semiconductor device in A3, wherein the active regions arefurther partitioned by two of the dummy word lines.

A5. The semiconductor device in A3 or A4, wherein the two groupsadjacent in the second direction have mutually symmetrical structuresusing the dummy word line as an axis.

A6. The semiconductor device according to any one of A1 to A5, whereinthe active regions are also divided by the first element isolationregions in the second direction so as to define the first and secondmemory cells.

A7. The semiconductor device in A2, further comprising:

a second element isolation region that is extended in the firstdirection, the first memory cell being sandwiched between the secondelement isolation region and the word line related to the first memorycell; and

a third element isolation region that is extended in the firstdirection, the second memory cell being sandwiched between the thirdelement isolation region and the word line related to the second memorycell, wherein

the active region is further defined by the second and third elementisolation regions from a viewpoint of the second direction, and

the first and second memory cells are included in the further definedactive region.

A8. The semiconductor device according to any one of A1 to A7 wherein anupper surface of the word line is located at a position lower than lowersurfaces of the first and second diffusion regions.

A9. The semiconductor device according to any one of A1 to A8, wherein asum of lengths of the second and third diffusion regions in a thirddirection that is perpendicular to the first and second directions issubstantially same as a length of the first diffusion region in thethird direction.

A10. The semiconductor device according to any one of A1 to A9, whereineach of the memory elements includes a phase-change memory element.

A11. The semiconductor device according to any one of A1 to A10, whereinan electric potential that brings the bipolar transistor into conductiveis supplied to the first diffusion region by turning the firstfield-effect transistor on.

A12. The semiconductor device according to any one of A1 to A11, furthercomprising a slit-shaped contact conductor that is extended in the firstdirection and is formed above a plurality of the first diffusionregions, and is connected to the first diffusion regions.

A13. The semiconductor device in A12, wherein the first elementisolation region is extended in the second direction below theslit-shaped contact conductor and crosses the slit-shaped contactconductor.

A14. The semiconductor device in A12 or A13, wherein the first elementisolation region is one of the plurality of the first diffusion regionscorresponding to the plural active regions formed respectively in thesecond direction.

A15. The semiconductor device according to any one of A1 to A14, whereinthe first diffusion region includes a salicide structure.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor substrate of a first conductivity type including a trenchhaving a bottom surface and an inner wall; a gate insulating film thatis formed on the bottom surface and a part of the inner wall of thetrench; a first gate electrode that is embedded in a lower portion ofthe trench so as to cover the gate insulating film; a first capinsulating film that is embedded in an upper portion of the trench so asto cover the first gate electrode; a first diffusion region that isformed in the semiconductor substrate and located on a first sidesurface of the first cap insulating film; a second diffusion region thatis formed in the semiconductor substrate and located on a second sidesurface of the first cap insulating film opposite to the first sidesurface; and a third diffusion region that is formed in thesemiconductor substrate located on the second side surface of the firstcap insulating film and located between an upper surface of thesemiconductor substrate and an upper surface of the second diffusionregion, wherein the first and second diffusion regions and the firstgate electrode constitute a first field-effect transistor, the secondand third diffusion regions and the semiconductor substrate constitute afirst bipolar transistor, the first field-effect transistor and thefirst bipolar transistor constitute a first selective element, the firstand second diffusion regions have a second conductivity type opposite tothe first conductivity type, and the third diffusion region has thefirst conductivity type.
 2. The semiconductor device as claimed in claim1, wherein an upper surface of the first gate electrode is located at aposition lower than lower surfaces of the first and second diffusionregions.
 3. The semiconductor device as claimed in claim 1, wherein asum of lengths of the second and third diffusion regions in aperpendicular direction that is perpendicular to the upper surface ofthe semiconductor substrate is substantially same as a length of thefirst diffusion region in the perpendicular direction.
 4. Thesemiconductor device as claimed in claim 1, further comprising a secondcap insulating film, wherein the second and third diffusion regions aresandwiched between the first and second cap insulating films.
 5. Thesemiconductor device as claimed in claim 4, further comprising a secondgate electrode that is covered with a lower surface of the second capinsulating film.
 6. The semiconductor device as claimed in claim 5,further comprising a fourth diffusion region, wherein the second capinsulating film is sandwiched between the second and fourth diffusionregions, and the second gate electrode is supplied with an electricpotential so as not to cause the second diffusion region and the fourthdiffusion region being electrically conductive.
 7. The semiconductordevice as claimed in claim 1, further comprising a memory element thatis electrically connected to the third diffusion region.
 8. Thesemiconductor device as claimed in claim 7, wherein the memory elementincludes a phase-change memory element.
 9. The semiconductor device asclaimed in claim 1, wherein an electric potential that brings the firstbipolar transistor into conductive is supplied to the first diffusionregion by turning the first field-effect transistor on.
 10. Thesemiconductor device as claimed in claim 9, further comprising a memoryelement that is electrically connected to the third diffusion region,wherein an electric potential at which electrons are passed to thememory element is supplied to the semiconductor substrate by turning thefirst bipolar transistor on.
 11. The semiconductor device as claimed inclaim 1, further comprising a second selective element that shares thefirst diffusion region and is constituted by a second field-effecttransistor and a second bipolar transistor each having a structuresymmetrical with the first selective element using the first diffusionregion as an axis.
 12. A semiconductor device comprising: asemiconductor substrate of a first conductivity type; a cap insulatingfilm that is embedded in the semiconductor substrate and has a firstside surface perpendicular to an upper surface of the semiconductorsubstrate, a second side surface opposite to the first side surface, anda lower surface opposite to the upper surface of the semiconductorsubstrate; a first gate electrode of which whole of a body thereof isembedded in the semiconductor substrate and that is covered with a thelower surface of the cap insulating film; a gate insulating film ofwhich whole of a body thereof is embedded in the semiconductor substrateand that is formed between the gate electrode and the semiconductorsubstrate; a first diffusion region that covers the first side surfaceof the cap insulating film; a second diffusion region that covers thesecond side surface of the cap insulating film; and a first selectiveelement that covers the second side surface of the cap insulating filmand an upper surface of the second diffusion region, and has a thirddiffusion region in contact with the upper surface of the semiconductorsubstrate, wherein the gate electrode and the first and second diffusionregions constitute a first field-effect transistor, the semiconductorsubstrate and the second and third diffusion regions constitute a firstbipolar transistor, the field-effect transistor and the first bipolartransistor constitute the first selective element, the first and seconddiffusion regions have a second conductivity type opposite to the firstconductivity type, and the third diffusion region has the firstconductivity type.
 13. The semiconductor device as claimed in claim 12,wherein an upper surface of the first gate electrode is located at aposition lower than lower surfaces of the first and second diffusionregions.
 14. The semiconductor device as claimed in claim 12, wherein asum of lengths of the second and third diffusion regions in aperpendicular direction that is perpendicular to the upper surface ofthe semiconductor substrate is substantially same as a length of thefirst diffusion region in the perpendicular direction.
 15. Thesemiconductor device as claimed in claim 12, further comprising a secondcap insulating film, wherein the second and third diffusion regions aresandwiched between the first and second cap insulating films.
 16. Thesemiconductor device as claimed in claim 15, further comprising a secondgate electrode that is covered with a lower surface of the second capinsulating film.
 17. The semiconductor device as claimed in claim 16,further comprising a fourth diffusion region, wherein the second capinsulating film is sandwiched between the second and fourth diffusionregions, and the second gate electrode is supplied with an electricpotential so as not to cause the second diffusion region and the fourthdiffusion region being electrically conductive.
 18. The semiconductordevice as claimed in claim 12, further comprising a memory element thatis electrically connected to the third diffusion region.
 19. Thesemiconductor device as claimed in claim 18, wherein the memory elementincludes a phase-change memory element.
 20. The semiconductor device asclaimed in claim 12, wherein an electric potential that brings the firstbipolar transistor into conductive is supplied to the first diffusionregion by turning the first field-effect transistor on.
 21. Thesemiconductor device as claimed in claim 20 further comprising a memoryelement that is electrically connected to the third diffusion region,wherein an electric potential at which electrons are passed to thememory element is supplied to the semiconductor substrate by turning thefirst bipolar transistor on.
 22. The semiconductor device as claimed inclaim 12, further comprising a second selective element that shares thefirst diffusion region and is constituted by a second field-effecttransistor and a second bipolar transistor each having a structuresymmetrical with the first selective element using the first diffusionregion as an axis.
 23. A semiconductor device comprising: asemiconductor substrate of a first conductivity type; a gate insulatingfilm on a bottom surface of the semiconductor substrate; a gateelectrode over the gate insulating film; a cap insulating film over thegate electrode; a first diffusion region located on a first side surfaceof the cap insulating film; a non-volatile memory including acylindrically shaped memory element; a bit line over the cylindricallyshaped memory element; and a selective element including a field-effecttransistor at a lower end of the cylindrically shaped memory element,the field-effect transistor including a first portion, a second portionand a horizontal channel portion, wherein the first portion of thefield-effect transistor has a cylindrical shape and is connectedintegrally to the semiconductor substrate, a top of the first portion ofthe field-effect transistor is located at a boundary between a topregion where the cylindrically shaped memory element is located and abottom region where the field-effect transistor is located, the topregion and the bottom region being different in either material orcrystallinity, the horizontal channel portion of the field-effecttransistor is located on a diffusion region of the semiconductorsubstrate having the first conductivity type, the second portion of thefield-effect transistor is located in the first diffusion region, and aslit-shaped contact conductor is located on the first diffused region,the second portion of the field-effect transistor and the slit-shapedcontact conductor extending in a direction perpendicular to the bitline, the first portion of the field-effect transistor has the firstdiffused region and the slit-shaped contact conductor at most on oneside, the first diffusion region and the first gate electrode constitutethe field-effect transistor, the field-effect transistor constitutes theselective element, and the first diffusion region has a secondconductivity type opposite to the first conductivity type.
 24. Thesemiconductor device as claimed in claim 23, further comprising aconductive line contacting at least two cylindrically shaped memoryelements, wherein the bit line connected on top of the conductive linethrough a contact conductor.
 25. The semiconductor device as claimed inclaim 23, wherein the first diffusion region and the slit-shaped contactconductor are electrically connected to a ground node.
 26. Thesemiconductor device as claimed in claim 23, wherein in at least oneoperation mode, a continuous current path is formed connecting the bitline through the cylindrically shaped memory element to the diffusionregion of the semiconductor substrate having the first conductivitytype.
 27. A semiconductor device comprising: a semiconductor substrateof a first conductivity type; a cap insulating film that has a firstside surface perpendicular to an upper surface of the semiconductorsubstrate, a second side surface opposite to the first side surface, anda lower surface; a first gate electrode covered with the lower surfaceof the cap insulating film; a gate insulating film formed between thegate electrode and the semiconductor substrate; a first diffusion regionthat covers the first side surface of the cap insulating film; anon-volatile memory including a cylindrically shaped memory element; abit line over the cylindrically shaped memory element; and a selectiveelement including a field-effect transistor at a lower end of thecylindrically shaped memory element, the field-effect transistorincluding a first portion, a second portion and a horizontal channelportion, wherein the first portion of the field-effect transistor has acylindrical shape and is connected integrally to the semiconductorsubstrate, a top of the first portion of the field-effect transistor islocated at a boundary between a top region where the memory element islocated and a bottom region where the field-effect transistor islocated, the top region and the bottom region being different either inmaterial or crystallinity, the horizontal channel portion of thefield-effect transistor is located on a diffusion region of thesemiconductor substrate having the first conductivity type, the secondportion of the field-effect transistor is in the first diffusion region,and a slit-shaped contact conductor is located on the first diffusedregion, the second portion of the field-effect transistor and theslit-shaped contact conductor extending in a direction perpendicular tothe bit line, the first portion of the field-effect transistor has thefirst diffused region and the slit-shaped contact conductor at most onone side, the gate electrode and the first diffusion region constitutethe field-effect transistor, the field-effect transistor constitutes theselective element, and the first diffusion region has a secondconductivity type opposite to the first conductivity type.
 28. Thesemiconductor device as claimed in claim 27, further comprising aconductive line contacting at least two cylindrically shaped memoryelements, wherein the bit line connected on top of the conductive linethrough a contact conductor.
 29. The semiconductor device as claimed inclaim 27, wherein the first diffusion region and the slit-shaped contactconductor are electrically connected to a ground node.
 30. Thesemiconductor device as claimed in claim 27, wherein in at least oneoperation mode, a continuous current path is formed connecting the bitline through the cylindrically shaped memory element to the diffusionregion of the semiconductor substrate having the first conductivitytype.